Ever-increasing speed requirements for memory access has resulted in the use of DDR architectures to achieve high-speed operation. The DDR architecture is used to transfer two data words per clock cycle between a memory controller and a DDR SDRAM. Source synchronous strobe signals are transmitted along with the data to enable capturing the data at the receiver. Series Stub Terminated Logic (SSTL—2) may be used for signaling as a JEDEC (Joint Electron Device Engineering Council) approved standard for DDR SDRAM—MCH (Memory Controller Hub) transactions. When there is no data transfer, the line is pulled to a high impedance state by the termination in accordance with this standard.
Transactions between the MCH and the DDR SDRAM are classified as READ transactions, WRITE transactions and other transactions. All transactions are referred to the memory controller. A READ cycle usually refers to the MCH reading data from the DDR SDRAM while a WRITE cycle usually refers to the MCH sending data to the DDR SDRAM.
When the MCH writes data into the DDR, it positions a data strobe signal (DQS) at the center of a valid data window. However, when the DDR SDRAM sends out data to the MCH, it edge aligns the data (DQ) and the DQS signals. When the DDR SDRAM receives an active READ command from the memory controller, it places the data and strobe edge aligned at the DDR. Prior to this, it pulls down the DQS signal line to a LOW logic level, typically for one clock period. This portion of the DQS signal is called the READ PREAMBLE. The READ PREAMBLE may vary plus or minus 10 percent, for example, from the clock period. Following the READ PREAMBLE, the rising and falling edges of the DQS signal are used for strobing in the data at the receiver.
However, a major shortcoming is that when the DDR SDRAM sends a READ PREAMBLE on the DQS signal line, the DQS line is transitioned to a LOW logic state from a high impedance state. During the time when the DQS line is in its high impedance state and during its transition to the LOW logic state, noise can cause the receiver to misinterpret noise pulses as a valid strobe, thereby causing the receiver to latch incorrect data. Accordingly, there is a need for a technique which can identify a valid READ PREAMBLE and subsequently use the validated PREAMBLE to latch the correct data at the receiver.
Furthermore, the existing DDR SDRAM protocol does not provide a feedback to the memory controller indicating when to look for the data strobe. Rather, the memory controller launches a READ command and then somehow identifies the arrival of the DQS strobe signal. This is usually accomplished by having additional pins at the memory controller for launching a reference signal which will track the DQS strobe signal. The launching of an active READ command, the CAS latency period, the flight time variation of the reference signal, the DQ-DQS skew information at the DDR SDRAM, etc., may be used to calculate a valid DQS window in which the DQS buffer is enabled. Such a technique is very much dependent on flight time uncertainties and imposes critical board routing constraints as well as requiring two additional pins which increases costs. Accordingly, there is also a need for a technique which uses built-in elements which form part of every DQS buffer and which is not dependent on arrival uncertainties of the DQS signal and does not impose severe board routing constraints.